via Direct to Device
Programme Overview
Programme Highlights
Certification from CEP, IIT Delhi
Learn from top faculty in VLSI Design
3 Days Campus Immersion
Real-world Case Studies
Industries Visits/Interactions with the Leaders
Networking Opportunities during Campus Immersion
Eligibility Criteria
- Any Electronics, Electrical, Physics or Computer Science Graduate.
- Candidates pursuing the graduation degree are also eligible however preference will be given to applicants with experience.
- Diploma holders (10 + 3) or (10 + 2 + 3) are also eligible.
Screening & Selection
- Screening and selection will be done by IIT Delhi.
Assessment
- 60% – End of programme MCQ-based exam
- 40% – Assignments & project
- 10% – Attendance (Grace)
- Candidates need to secure a minimum of 50% overall to be eligible for the certificate.
Attendance
- Minimum of 50% attendance is mandatory.
Syllabus Breakdown
- CMOS ASIC Design Flow
- CMOS Circuit Design
- Delay, Setup and Hold Time Analysis
- Combinational and Sequential Circuits
- High Performance Design
- Low-Power Design
- CMOS Standard Cells, GPIOs
- Custom blocks e.g. Level-shifters
- Power Management (PMIC) Blocks
- RTL implementation and Verification
- Design Synthesis
- DFT, Scan and ATPG
- Floor-Plan
- Placement
- Static Timing Analysis
- Clock Tree Synthesis and Signal Integrity
- Routing and DRC
- Layout Parasitic Extraction
- Unix Environment
- Shell/Tcl/Perl/Python Scripting
- Verilog Model Development
- Post Silicon Chip Validation
- Chip Integration and Packaging
- Interview FAQs
- 24 hours of Lab module is planned in the programme.
- Labs will be conducted online. Various projects and hands-on training will be provided during lab hours.
- Circuit Simulation Tool: LTSpice
- Verilog Simulation Tool: ModelSim
- FPGA/RTL Design Tool: Xilinx Vivaldo
- FPGA Development Tool: Quartus Prime Lite
- Operating System and Languages: Linux/Tcl
Some of the projects planned are given below:
- Project 1: Combinational and Sequential CMOS Circuit Design
- Project 2: CMOS Low Power I/O Circuit Design
- Project 3: Power Management IC (PMIC) Design
- Project 4: Clock Tree Synthesis and Static Timing Analysis
- Project 5: Design for Test (DFT) and Automatic Test Pattern Generation (ATPG)
About IIT Delhi
About Continuing Education Programme (CEP)
2nd Rank
as per NIRF India
Engineering Rankings (2024)
2nd Rank
as per QS World
University Ranking
(2024) in India
Programme Coordinator
Programme Certification
- Candidates who score at least 50% marks overall and have a minimum attendance of 50% will receive a ‘Certificate of Completion’ from CEP, IIT Delhi.
- Participants who are unable to score 50% marks in the evaluation but maintain a minimum attendance of 50% will be eligible for the ‘Participation Certificate’ from CEP, IIT Delhi.
- The above e-certificate is for illustrative purposes only and the format of the certificate may be changed at the discretion of IIT Delhi.
- Only e-certificate will be provided and it will be issued by CEP, IIT Delhi.
- The organizing department of this programme is the Centre for Applied Research in Electronics (CARE) at IIT Delhi.
Programme Fee Details
3 days from date of offer
4th October 2024
Easy EMI Options Available*
- *Payment of fees should be submitted in the IIT Delhi CEP account only and the receipt will be issued by the IIT Delhi CEP account for your records.
- *Loan Options is a service offered by Jaro Education. IIT Delhi is not responsible for the same.
The Jaro Advantage
- Unparalleled career guidance and support
- Dedicated student support
- Immersive and lifelong learning experiences
- Learn from the best-suited academic, faculty, and industry mentors
- Be a part of discussions and forums for enhanced learning
- Leverage peer-to-peer learning experience
- Alumni Network of 3,50,000+ Professionals
- Access to alumni events & other benefits
- Stay up to date with the latest insights from your alma mater
Jaro Expedite - Career Booster
Profile Building
Rigorously building the candidate’s profiles and resume scrutinizing their LinkedIn profiles. Jaro Education enables personalised feedback to boost overall virtual presence.
Resume Review
Moving forward with carefully curated resume reviews that ensures you are interview-ready for the workplace of tomorrow.
Placement Assistance
Get career assistance as per the profile and preferences. On average, get 5-6 job recommendations to enhance quality employment opportunities.
Career Enhancement Sessions
Bridging connectivity to link the best talent with organizations through eminent sessions from top-class industry speakers.
Note: IIT Delhi or Jaro Education do not guarantee or promise you a job or advancement in your existing position. Career Services is simply provided as a service to help you manage your career in a proactive manner. Jaro Education provides the Career Services described here. IIT Delhi is not involved in any way with the Career Services described above and offer no commitments.
Build 21st-Century Skill set to Gain Career Edge in the VUCA World
You’ll learn
- Demonstrate a solid understanding of design principles, including logic synthesis, timing analysis, and physical design.
- Utilize industry-standard VLSI design softwares to design, simulate, and verify digital integrated circuits.
- Apply advanced VLSI design techniques such as low-power design, high-speed design, and design for testability (DFT).
- Analyze and optimize the performance, area, and power consumption of digital VLSI designs.
- Work effectively in interdisciplinary teams to tackle real-world VLSI design challenges and projects.
- This programme in Digital VLSI Design offers hands-on exposure to industry-standard tools and methodologies, along with practical design projects and case studies, which enhance problem-solving capabilities and readiness to tackle real-world design challenges.
- Participants will gain exposure to industry-standard tools such as CAD tools, hardware description languages (HDLs), simulation tools, and scripting languages like Shell, Tcl, Perl, and Python. They will also learn about design synthesis, DFT, scan, ATPG, and other essential methodologies in digital VLSI design.
- The lab module consists of 24 hours of online sessions where participants engage in hands-on projects and training related to digital VLSI design. Various projects, including Combinational and Sequential CMOS Circuit Design, Power Management IC Design, and Clock Tree Synthesis, are planned to provide practical experience.
Following are some of the ideal career prospects
- Digital VLSI Design Engineers: Participants can embark on careers involving the design and development of digital integrated circuits, focusing on optimizing performance and efficiency.
- ASIC Designers: Learners can pursue roles specializing in Application-Specific Integrated Circuit (ASIC) design, tailoring circuits to specific applications or functionalities.
- Verification Engineers: Opportunities exist in verification engineering, where participants ensure the functionality and correctness of digital designs through rigorous testing and validation processes.
- Academic Research: Those inclined towards academia can engage in further research in digital VLSI design, contributing to advancements in the field through innovative research projects and publications.
Potential career paths include VLSI Designer, VLSI Test Engineer, Digital System Analyst, and IC Verification Engineer. The job market for individuals with Digital VLSI Design skills is promising, with increasing demand due to technology advancements. Moreover, opportunities in academia, research, and development are also available for experts in this field.
- The total programme fee is INR 1,20,000/- + GST. Interested individuals are encouraged to connect with Jaro Education’s admission experts for more information on the enrollment procedure.